Method to reduce dishing and erosion in a CMP process

ABSTRACT

A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.

FIELD OF THE INVENTION

[0001] This invention generally relates to CMP polishing methods andmore particularly to a method for polishing an oxide layer adjacent tocopper filled semiconductor features included in semiconductor waferprocess surface to reduce copper feature dishing and oxide erosion.

BACKGROUND OF THE INVENTION

[0002] Planarization is increasingly important in semiconductormanufacturing techniques. As device sizes decrease, the importance ofachieving high resolution features through photolithographic processescorrespondingly increases thereby placing more severe constraints on thedegree of planarity required of a semiconductor wafer processingsurface. Excessive degrees of surface non-planarity will undesirablyaffect the quality of several semiconductor manufacturing processincluding, for example, photolithographic patterning processes, wherethe positioning the image plane of the process surface within anincreasingly limited depth of focus window is required to achieve highresolution semiconductor feature patterns.

[0003] In the formation of conductive interconnections, copper isincreasingly used for forming metal interconnects such as vias andtrench lines since copper has low resistivity and good electromigrationresistance compared to other traditional interconnect metals such asaluminum. The undesirable contribution to electrical parasitic effectsby metal interconnect residual resistivity has become increasinglyimportant as device sizes have decreased. One problem with the use ofcopper relates to it relatively high degree of softness making itsubject to relatively high differential material removal rates comparedto adjacent dielectric insulating oxide materials during planarizationprocesses such as chemical mechanical polishing (CMP).

[0004] Copper chemical mechanical planarization (CMP) is an importantaspect of successful electrochemical deposition (ECD) processes wherecopper and copper barrier layers deposited overlying copper filledfeatures are subsequently removed by a CMP planarization process. Bothlocal and global planarization is critical to successful deviceoperation especially with respect to forming overlying integrated devicefeatures. A recurring problem in copper CMP processes is that thesimultaneous goal of achieving fast material removal rates of the copperand the underlying barrier layer without erosion of the underlyinginsulating dielectric layer or dishing of the copper filled feature isdifficult to attain. Typically, the excess copper layer is removedfollowing ECD according to a CMP process which generally includes anabrasive polishing slurry and a polishing pad applied with a significantdown force to the semiconductor wafer surface. Typically multiple CMPpolishing steps are used to first remove the copper layer followed byremoval of the barrier layer to reveal an oxide layer and typicallyincluding a final oxide layer buffing step. In the prior art separateslurries are used for the individual CMP polishing steps to achieve thedesired selectivity and removal rates. For example, it is frequentlydesirable to first use a slurry with a high copper removal rate tominimize the required polishing time for relatively thick overlayers ofexcess copper. The high removal rate slurry is then replaced with a lowor medium removal rate slurry and polishing system including a differentpolishing pad to remove the barrier layer at a slower rate to reduceerosion of the underlying oxide layer and to reduce copper dishing.

[0005] The planarity of CMP processes is increasingly criticalespecially for devices having narrow semiconductor features such as linewidths below about 0.25 micron. CMP planarization is typically usedseveral different times in the manufacture of a multi-levelsemiconductor device, including planarizing levels of a devicecontaining both dielectric and metal portions to achieve local andglobal planarization for subsequent processing of overlying levels.Several semiconductor wafer defects are associated with non-planaritiesintroduced during CMP polishing. For example, in CMP polishing of highpolish rate materials such as copper features adjacent to an oxidesurface, uniform polishing or local planarization is highly dependent onfeature density. For example, the material removal rate isproportionally faster over larger surface areas of high polish ratematerial leading to dishing. In addition, a high pattern density (smallpitch) of metal filled features adjacent to lower polish rate materialssuch as nitrides or oxides can lead to both dishing and erosion over thepatterned area. Generally, erosion is defined as the thinning of theoxide layer thickness, for example, a low-k (low dielectric constant)oxide material including metal filled features, relative to anunpatterned or lower pattern density area. Dishing is defined as thereduced thickness of the metal feature from the lowest point of thefeature relative to the adjacent oxide layer. Therefore the sum of theerosion and dishing represents total metal removal. Although erosion ofnarrow copper features in a relatively densely patterned area of a waferprocess surface is known and various approaches have been proposed toreduce erosion, dishing of the relatively narrow line width copperfeatures remains a problem which can degrade device electricalreliability and performance. One approach to improving planarity andreducing erosion has been to use slurries having higher selectivity'sfor material removal of the target layer with respect to an underlyinglayer.

[0006] For example, highly selective polishing slurries for polishingthe various layers are available commercially and formulated forpolishing the particular targeted polishing layer, for example a copperlayer overlying an adhesion/barrier layer and a tantalum nitride (e.g.,TaN) barrier layer overlying an oxide layer, for example an insulatingdielectric layer or an oxide capping layer. High selectivity slurriesmay include various metal oxide abrasives including for example, silica(SiO₂), alumina (Al₂O₃), ceria (CeO₂), titania (TiO₂), manganese dioxide(MnO₂), and zirconia (ZrO₂). In addition, complexing agents andsurfactants are typically used to facilitate interaction of the slurryabrasive with the targeted polishing surface.

[0007] The increased use of lower strength low-k materials for theinsulating dielectric layer, also referred to as an inter-layerdielectric (ILD) layer or inter-metal dielectric (IMD) layer, has led toincreased vulnerability of oxide erosion resulting in surface topographyvariations caused by slurries having less than adequate selectivity'swith respect to an underlying layer, for example a TaN adhesion/barrierlayer overlying an oxide based layer, for example an ILD layer, ananti-reflectance coating (ARC) layer, or an oxide capping layer. Aspointed out, one approach in the prior art to reduce erosion of anunderlying oxide layer has been to use slurries with higherselectivity's with respect to the underlying layer, for example inpolishing a barrier layer overlying an oxide layer. One problem withthis approach is that the high selectivity slurries formulated forpolishing the particular layers frequently also have copper removalrates resulting in dishing of relatively narrow copper features leadingsubsequent processing difficulties and device electrical performancedegradation. Generally, both erosion and dishing lead to severalsubsequent processing difficulties such as forming overlying layerfeatures with adequate integrated electrical connectivity, as well asoptical resolution issues in photolithographic patterning steps. Assuch, it has been difficult to develop CMP polishing methods that canaccomplish both requirements of reduced oxide layer erosion and copperfeature dishing.

[0008] Therefore, there is a need in the semiconductor art for animproved CMP polishing method whereby a CMP polishing step including aCMP polishing slurry is better optimized for polishing copper filledfeatures adjacent to an oxide surface to avoid the problems of dishingof the copper filled features while avoiding oxide erosion.

[0009] It is therefore an object of the invention to provide an improvedCMP polishing method whereby a CMP polishing step including a CMPpolishing slurry is better optimized for polishing copper filledfeatures adjacent to an oxide surface to avoid the problems of dishingof the copper filled features while avoiding oxide erosion in additionto overcoming other shortcomings and deficiencies in the prior art.

SUMMARY OF THE INVENTION

[0010] To achieve the foregoing and other objects, and in accordancewith the purposes of the present invention, as embodied and broadlydescribed herein, the present invention provides a CMP process forselectively polishing an overlying material layer with respect to anunderlying layer comprising at least one material in a semiconductordevice fabrication process.

[0011] In a first embodiment, the method includes providing asemiconductor wafer process surface including a first material layeroverlying at least a second layer including at least one material;mixing at least two slurry mixtures including a first CMP slurryformulation optimized for removing the first material layer and a secondCMP slurry formulation optimized for removing the at least a secondlayer to form a slurry formulation mixture; and, carrying out a CMPprocess using the slurry formulation mixture to remove the firstmaterial layer and at least a portion of the at least a second layer.

[0012] These and other embodiments, aspects and features of theinvention will be better understood from a detailed description of thepreferred embodiments of the invention which are further described belowin conjunction with the accompanying Figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIGS. 1A-1E are cross sectional side view portions of asemiconductor feature included in a process wafer at stages ofmanufacture according to an embodiment of the present invention.

[0014]FIG. 2 is a process flow diagram including several embodiments ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Although the CMP process according to present invention isexplained with reference to copper semiconductor features formed in alow-k dielectric material layer associated with a multilayersemiconductor device, it will be appreciated that the CMP process may beadvantageously used in a CMP process to polish copper semiconductorfeatures having adjacent oxide containing material surfaces includingrelatively higher dielectric constant material layers. In addition,although the method of the present invention is explained with referenceto narrow copper filled semiconductor feature, for example a copperfiled damascene less having a line width of less than about 0.25microns, it will be appreciated that the CMP process may advantageouslybe used for polishing any copper filled semiconductor feature where itwould be advantageous to reduce dishing of the copper feature during theCMP process including polishing an adjacent oxide containing materialsurface adjacent the damascene feature including vias and dual damascenefeatures. In addition, while the CMP process of the present invention isadvantageously used to polish a copper filled damascene feature it willbe appreciated that the CMP process may advantageously be used withother metal filled (damascene) features to achieve the goals of reducingdishing in relatively narrow line width metal filled semiconductorfeatures. As used herein, the term “copper” is means copper and alloysthereof. The term “low-k” means having a dielectric constant of lessthan about 3.2.

[0016] In a first embodiment of the invention a first material layer isprovided forming a semiconductor wafer process surface overlying atleast a second material layer. A first CMP slurry formulation optimizedfor removing the first material layer is then mixed with a second CMPslurry formulation optimized for removing the at least a second materiallayer to form a slurry formulation mixture. A CMP process using theslurry formulation mixture is then carried out to remove the firstmaterial layer and the at least a second material layer. In oneembodiment, the first and second CMP slurry formulations are optimizedby having a relatively higher material removal rate of the firstmaterial layer compared to a material removal rate of the at least asecond material removal rate.

[0017] In another embodiment, the at least a second material layerincludes a metal filled feature adjacent to an oxide containing surfacewhich is a third material layer (e.g., second material in second layer,for example metal filled damascene). The second CMP slurry formulationis optimized by having a third material layer removal rate that isrelatively greater compared to the second material layer removal rate.

[0018] In one embodiment, the slurry formulation mixture is formed bymixing a volumetric ratio of the first CMP slurry formulation withrespect to the second CMP slurry formulation from about 1:10 to about10:1, more preferably about 1:2 to about 2:1 with respect to the totalvolume of the slurry formulation mixture.

[0019] In another embodiment, the slurry formulation mixture exhibits anincreased removal rate of the first material layer removal rate withrespect to at least one of the second and third material layer removalrates.

[0020] Referring to FIG. 1A, in an exemplary implementation of thepresent invention an array of metal filled interconnect features, forexample trench lines e.g., 12, having a line width of less than about0.25 microns are formed in a dielectric insulating layer 14 by aconventional anisotropic etching and photolithographic patterningprocess. For example, the dielectric insulating layer 14 is a silicondioxide based material, for example a carbon doped silicon dioxide, alsoreferred to as organo silicate glass (OSG) and C-oxide. Severalcommercially available formulations are available for producing thelow-k carbon doped oxide, for example, known as SILK™ and BLACKDIAMOND™. In addition, the carbon doped oxides may be produced by plasmaenhanced CVD methods using organo-silane precursors such asocta-methyl-cyclo-tetra-siloxane and tetra-methyl-cyclo-tetra-siloxanewhere the dielectric constant may be varied over a range depending onthe precursors and process conditions. C-oxide, for example, may beformed with dielectric constants over a range of about 2.0 to about 3.0having a density of about 1.3 g/cm³. Other types of low-k materialssuitably used with the method of the present invention as dielectricinsulating layers, also referred to as inter-layer dielectric (ILD)layers, include fluorinated silicate glass (FSG) and porous oxides.

[0021] It will be appreciated that organic ILD layers may beadvantageously used in the method of the present invention where anoxide based capping layer or anti-reflectance coating (ARC) is providedover the ILD layer. Exemplary organic low-k materials includepolyarylene ether, hydrogen silesquioxane (HSQ), methyl silsesquioxane(MSQ), polysilsequioxane, polyimide, benzocyclobutene, and amorphousTeflon.

[0022] Still referring to FIG. 1A, overlying the ILD layer 14 is formedan oxide based layer 16, for example including at least one of an SiO₂capping layer to protect the underlying ILD layer, an oxide etching stoplayer, for example silicon oxynitride (e.g., SiON), and an ARC layer,for example silicon oxynitride (e.g., SiON), to reduce standing wavereflections in a subsequent photolithographic patterning process. Forexample, the oxide layer 16 (e.g., ARC layer) is from about 500Angstroms to about 1500 Angstroms in thickness.

[0023] Still referring to FIG. 1A, a barrier layer 18A formed of, forexample, a refractory metal including at least one of tantalum,titanium, and tungsten, and nitrides thereof including multiple layerssuch as a metal/metal nitride layer, is blanket deposited to line theetched trench features 12 at a thickness of about 50 Angstroms to about150 Angstroms. The barrier layer 18A serves the purpose of preventingsubsequently deposited copper from diffusing into the surrounding ILDlayer 14 and improves adhesion of the copper.

[0024] Still referring to FIG. 1A, following deposition of barrier layere.g., 18A, a copper layer 18B is electroplated according to aconventional electrochemical deposition (ECD) process to fill the trenchline features, 12 including an overlayer above the trench level of about400 Angstroms to about 6000 Angstroms. It will be appreciated that othermetals including tungsten, aluminum and aluminum copper alloys maysuitably be used with the method of the present invention but is mostadvantageously used with a copper. Prior to electrodeposition, a seedlayer of copper (not shown) is deposited over the barrier layer 18A by,for example by PVD or CVD. The copper seed layer is preferably depositedto form a continuous layer thereby providing a continuously conductivesurface for the bulk copper ECD process.

[0025] Referring to FIG. 1B, in an exemplary embodiment of the methodaccording to the present invention, a first CMP process is first carriedout to remove at least a portion of the excess copper layer 18Boverlying the barrier layer 18A for example leaving about 1500 Angstromsto about 2500 Angstroms overlying the barrier layer 18A. The first CMPprocess preferably uses a slurry and polishing pad optimized for a highremoval rate of copper, for example from about 4000 Angstroms/minute toabout 8000 Angstroms/minute. In a second CMP process, a slurry isoptimized for removal of copper with high selectivity to the underlyingbarrier layer 18A is used to remove a remaining portion of copperoverlying the barrier layer to reveal at least a portion of the barrierlayer 18A. For example, the CMP slurry used in the second CMP processhas a material removal rate of copper with respect to the barrier layerof from about 10:1 to about 50:1. Several formulations of commerciallyavailable polishing slurries having the preferred selectivity areavailable. For example, the removal rate of copper in the first CMPprocess is about 4000 Angstroms/minute to about 8000 Angstroms/minutewith the second CMP process having a copper removal rate slower by about20 percent to about 50 percent.

[0026] Referring to FIG. 1C, in one embodiment, the second CMP processis carried out to endpoint detection of the barrier layer 18A underlyingthe copper layer 18B. By the term ‘endpoint detection’ is meant thatpoint at which a portion of the underlying layer, for example thebarrier layer, is revealed in the polishing process sufficient to bedetected by an endpoint detecting means. Endpoint detection may beaccomplished by any process however, preferably, the endpoint detectionprocess detects a point in the CMP process at which a portion of thewafer polishing surface includes exposure of a portion of the underlyinglayer, for example the barrier layer 18A, and a portion of the overlyinglayer, for example the copper layer 18B. For example, preferably, atendpoint detection there will be portions of the semiconductor processsurface where the barrier layer is exposed and portions where the copperoverlayer remains. Exemplary endpoint detection systems known in the artthat may suitably be used include, for example, real-time opticaldetection methods including wafer polishing surface reflectancemeasurements, as well as laser interferometry. In addition, methods suchas polishing pad motor load monitoring, or monitoring the electricalpotential of the polishing effluent may be suitably used for endpointdetection.

[0027] Referring to FIG. 1D, in a third CMP process, a CMP slurry(barrier layer slurry) having a material removal rate of the barrierlayer 18A about equal to or greater compared with the underlying oxidelayer 16 and a greater material removal rate with respect to the copperfilled trench lines e.g., 12A, is used to remove a remaining portion ofthe remaining copper and a portion of the barrier layer to reveal atleast a portion of the underlying oxide surface 16, e.g., an ARC layer.Preferably, the barrier layer slurry has a material removal rate ratiowith respect to the material removal rate of the underlying copper layerof about 2:1 to about 12:1.

[0028] Referring to FIG. 1E, in a fourth CMP process according to anembodiment of the present invention is carried out to remove a remainingportion of the barrier layer 18A and the underlying oxide layer 16(e.g., ARC layer) to reveal a portion of the underlying ILD layer usinga mixture of the barrier layer slurry (third CMP slurry) and an oxidepolishing slurry to form a mixed formulation slurry. For example, theoxide polishing slurry preferably has a material removal rate ratiocompared to a copper removal rate of about 2:1 to about 10:1. Preferablyoxide polishing slurry is formulated such the removal rate of thebarrier layer compared to the oxide removal rate is about equal to orless than the oxide material removal rate. In a preferred embodiment,the slurry formulation mixture has a volumetric ratio of the barrierlayer polishing slurry to the oxide polishing slurry of about 1:10 toabout 10:1, more preferably from about 1:2 to about 2:1. Preferably, theslurry formulation mixture has a material removal rate of the oxidelayer (ARC layer) compared to the copper removal rate that is greaterthan either of the third CMP slurry and oxide polishing slurry (fourthslurry) used alone. Preferably, at least one of the barrier layer slurry(third CMP slurry) and the oxide polishing slurry (fourth CMP slurry)include at least one nitrogen containing chelating agent to form themixed formulation slurry.

[0029] A copper corrosion inhibitor, for example BTA is preferably addedto cover the exposed copper features prior to at least carrying out afifth CMP process for buffing the oxide using a slurry formulationhaving a material removal rate ratio of oxide compared to a removal rateof copper of at least 2:1 to about 10:1. However, the copper corrosioninhibitor may be optionally added prior to the third or fourth CMPprocess. Preferably, the copper corrosion inhibitor solution includes atleast one of Benzotriazole (BTA), and Benzotriazole derivatives such asTriazole, and Tritriazole. BTA is preferred as it has been found to bethe most effective copper corrosion inhibitor. The copper corrosioninhibitor solution preferably includes a mixture of BTA and deionizedwater including a concentration of BTA from about 0.02 weight percent toabout 0.1 weight percent. It will be appreciated that the corrosioninhibitor may be optionally added prior to the fourth CMP process.

[0030] Referring to FIG. 2 is a process flow diagram including severalembodiments of the present invention. In process 201, a semiconductorwafer process surface having a copper filled semiconductor feature withan overlying layer of blanket deposited copper is provided. In process203 a first CMP process is carried out using a first CMP slurry toremove a portion of the copper overlayer. In process 205, a second CMPprocess is carried out to endpoint detection of an underlying barrierlayer using a second CMP slurry having a copper material removal rategreater than a barrier layer removal rate. In process 207, a third CMPprocess is carried out to at least partially reveal an underlying oxidelayer using a third CMP slurry having a barrier layer removal rategreater than a copper removal rate according to preferred embodiments.In process 209, a fourth CMP process is carried out to remove aremaining portion of the barrier layer and the underlying oxide layer toreveal the underlying ILD layer using a fourth CMP slurry includingusing a mixture of the third CMP slurry and an oxide polishing slurryaccording to preferred embodiments. In process 211, an oxide buffingprocess is carried out using a fifth CMP process for buffing the oxideusing a slurry formulation according to preferred embodiments. Asindicated by process 213, a copper corrosion inhibitor such as BTA isadded to form a passivation layer over the copper filled features priorto at least one of the fourth and fifth CMP processes.

[0031] According to the CMP process of one embodiment of the presentinvention, it has been found that using the mixed formulation slurry inthe fourth polishing process produces a synergistic effect to increase aremoval rate of the oxide layer compared to a removal rate of coppercompared to the oxide polishing slurry alone by greater than about 100percent, thereby reducing both erosion and dishing to reduce totalcopper feature removal by about greater than 50 percent. Although theprecise reason for the synergistic effect is not presently clear it isbelieved to be related to the interaction of chelating agents typicallyused to chelate oxide materials present in the oxide polishing slurryand chelating agents typically used to chelate metal or metal nitridematerials present in the barrier layer polishing slurry.

[0032] The preferred embodiments, aspects, and features of the inventionhaving been described, it will be apparent to those skilled in the artthat numerous variations, modifications, and substitutions may be madewithout departing from the spirit of the invention as disclosed andfurther claimed below.

What is claimed is:
 1. A CMP process for selectively polishing anoverlying material layer with respect to an underlying surfacecomprising at least two materials comprising the steps of: providing asemiconductor wafer process surface comprising a first material layeroverlying a second material layer and a third material layer penetratingsaid first and second material layers; mixing at least two slurrymixtures to form a slurry formulation mixture comprising a first CMPslurry formulation having a first material removal rate for removing thefirst material layer and a second CMP slurry formulation having a secondmaterial removal rate for removing the second material layer; and,carrying out a CMP process using the slurry formulation mixture toremove the first material layer and at least a portion of the secondmaterial layer.
 2. The method of claim 1, wherein the slurry formulationmixture first comprises a relatively lower material removal rate of therespective first material layer and the second material layer comparedto the third material layer when compared to either of the first andsecond CMP slurry formulations.
 3. The method of claim 1, wherein thefirst CMP slurry formulation comprises at least a first chelating agentand the second CMP slurry formulation comprises at least a secondchelating agent.
 4. The method of claim 1, wherein third material layercomprises a metal adjacent to the second material layer comprising anoxide containing material.
 5. The method of claim 4, wherein the oxidecontaining material comprises at least one of a capping layer, an ARClayer, and an ILD layer.
 6. The method of claim 4, wherein the thirdmaterial layer comprises a copper filled damascene structure.
 7. Themethod of claim 4, wherein the first material layer includes at leastone of a refractory metal and refractory metal nitride.
 8. The method ofclaim 4, wherein the second CMP slurry formulation removes the metal ata removal rate compared to the second material layer removal rate by aratio of about 1:2 to about 1:12.
 9. The method of claim 8, wherein thefirst CMP slurry formulation removes the metal at a removal ratecompared to the second material layer removal rate about 1:2 to about1:10.
 10. The CMP process of claim 9, wherein the slurry formulationmixture removes the metal at a reduced rate compared to the second CMPslurry formulation.
 11. The method of claim 1, wherein the slurryformulation mixture is formed by mixing a volumetric ratio of the firstCMP slurry formulation with respect to the second CMP slurry formulationfrom about 1:10 to about 10:1 with respect to the total volume of theslurry formulation mixture.
 12. The method of claim 4, wherein theslurry formulation mixture produces a reduced metal material removalrate compared to the second material layer.
 13. A method for selectivelypolishing a barrier layer and an underlying ARC layer surrounding acopper filled trench in a CMP process comprising the steps of: providinga semiconductor wafer process surface comprising a trench formed in adielectric insulating layer having an uppermost anti-reflectance coating(ARC) layer, a blanket deposited barrier layer lining the trenchoverlying the ARC layer, and a blanket deposited copper layer fillingthe trench and overlying the barrier layer; carrying out a first CMPprocess for removing the copper layer to reveal a portion of the barrierlayer using a first CMP slurry according to an endpoint detection means;carrying out a second CMP process to remove at least a portion of thebarrier layer to expose the ARC layer using a second CMP slurry whereinthe barrier layer removal rate is greater than the ARC layer removalrate said barrier layer and said ARC layer in contact adjacent saidtrench; and, carrying out a third CMP process to remove a remainingportion of the barrier layer to include at least a portion of the ARClayer using a slurry mixture comprising the second CMP slurry and athird CMP slurry wherein an ARC layer removal rate is greater then acopper removal rate.
 14. The method of claim 13, wherein the slurrymixture has an increased ARC layer removal rate compared to the copperremoval rate compared to using the third CMP slurry alone.
 15. Themethod of claim 13, wherein the second CMP slurry has a ratio of thebarrier layer removal rate to the copper removal rate of about 2 to 1 toabout 12 to
 1. 16. The method of claim 13, wherein the third CMP slurryhas a ratio of the ARC layer removal rate to the copper removal rate ofabout 2 to 1 to about 10 to
 1. 17. The method of claim 14, wherein theslurry mixture has a ratio of the ARC layer removal rate to the copperremoval rate of about 2 to 1 to about 12 to
 1. 18. The method of claim13, further comprising a fourth CMP polishing step using the third CMPslurry to remove a remaining portion of the ARC layer to expose thedielectric insulating layer.
 19. The method of claim 18, furthercomprising an oxide buffing step following the fourth CMP process. 20.The method of claim 19, wherein a copper corrosion inhibitor comprisingat least one of Benzotriazole (BTA), derivatives thereof, and a nitrogencontaining chelating agent is added to the semiconductor wafer surfaceto form a passivation layer over the copper features prior to at leastone of the second, third and fourth CMP processes, and the oxide buffingstep.
 21. The method of claim 13, wherein the second CMP slurrycomprises a first chelating agent and the third CMP slurry comprise atleast a second chelating agent.
 22. The method of claim 21, wherein thefirst and second chelating agents interact in the slurry mixture toreduce a copper material removal rate.
 23. A chemical mechanical polish(CMP) process for preventing erosion of copper interconnect features ina semiconductor manufacturing process comprising the steps of: providinga semiconductor wafer process surface comprising a trench formed in adielectric insulating layer having an uppermost anti-reflectance coating(ARC) layer, a blanket deposited barrier layer lining the trenchoverlying the ARC layer, and a blanket deposited copper layer fillingthe trench and overlying the barrier layer; performing a first CMPprocess comprising a first CMP slurry solution to remove a first portionof a blanket deposited copper layer such that a remaining thicknessportion of the copper layer above the trench level is less than about200 Angstroms; performing a second CMP process comprising a second CMPslurry solution to remove a second portion of the copper layer to exposethe barrier layer; performing a third CMP process comprising a third CMPslurry solution to remove a first thickness portion of the barrier layerto expose the ARC layer; performing a fourth CMP process comprising amixture of the third CMP slurry solution and a fourth CMP slurrysolution to remove a portion of the ARC layer and a remaining portion ofthe barrier layer to expose the dielectric insulating layer; and,performing a fifth CMP process comprising said fourth CMP slurrysolution for removing a remaining portion of the ARC layer.